diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-05-15 19:27:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-15 19:27:00 +0200 |
| commit | a7281930c5877b34e072d90d5ca013f8fda7e2cc (patch) | |
| tree | b58a6b18cd643cadd0954207447b925d7fa67c66 /frontends/verilog | |
| parent | 4b6c0e331d0ef4188f8fa2443f8f7999231af052 (diff) | |
| download | yosys-a7281930c5877b34e072d90d5ca013f8fda7e2cc.tar.gz yosys-a7281930c5877b34e072d90d5ca013f8fda7e2cc.tar.bz2 yosys-a7281930c5877b34e072d90d5ca013f8fda7e2cc.zip | |
Fix handling of anyconst/anyseq attrs in VHDL code via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions