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authorEddie Hung <eddie@fpgeh.com>2019-07-02 10:21:10 -0700
committerEddie Hung <eddie@fpgeh.com>2019-07-02 10:21:10 -0700
commitc35023d0bf25fc12b09dea6b43ca28639b710078 (patch)
treef48be13fcdea803813a62d2a9d7c06fbd5d2e895 /frontends/verilog
parent879ae9d5538aa8661198e0714ba0c379646591fa (diff)
parent8455d1f4ffb942c802b65e20748e54a123e08df0 (diff)
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Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'frontends/verilog')
-rw-r--r--frontends/verilog/verilog_lexer.l2
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d3fd91473..951d9c66f 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END
to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
global state.. its a mess) */
[a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
+ if (!strcmp(yytext, "default"))
+ return TOK_DEFAULT;
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
return TOK_SVA_LABEL;
}