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| author | Claire Wolf <clifford@clifford.at> | 2020-04-02 18:15:15 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-02 18:15:15 +0200 |
| commit | c69f4b246aee8aa5841cc621de8c439fb4d40ed4 (patch) | |
| tree | 26da75be8931c4fb039ae526da8041e735556021 /frontends/verilog | |
| parent | 2d3753d730c99ab2c0253be119b04cec413e10ba (diff) | |
| parent | c859bcf71bddbcceb36d276221a5eb490ed1cf4c (diff) | |
| download | yosys-c69f4b246aee8aa5841cc621de8c439fb4d40ed4.tar.gz yosys-c69f4b246aee8aa5841cc621de8c439fb4d40ed4.tar.bz2 yosys-c69f4b246aee8aa5841cc621de8c439fb4d40ed4.zip | |
Merge pull request #1846 from dh73/ast_fe
Adding error message for when size (width) of number literal is zero
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 49281f7e7..230dfadbf 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -139,6 +139,9 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le data.resize(len_in_bits, msb); } + if (len_in_bits == 0) + log_file_error(current_filename, get_line_num(), "Illegal integer constant size of zero (IEEE 1800-2012, 5.7).\n"); + if (len > len_in_bits) log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n", len_in_bits, len, current_filename.c_str(), get_line_num()); |