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| author | whitequark <whitequark@whitequark.org> | 2019-11-18 09:37:14 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-18 09:37:14 +0000 |
| commit | cdb566b2d6a998ccaf5406f584e3ec810973dff9 (patch) | |
| tree | 0c507eb7b8383de0d5763b1fca77743c27c1f5f3 /frontends/verilog | |
| parent | 527434de493f88d5da64ae216df3b5a85558e47b (diff) | |
| parent | 3c643c57dfee9956697e8629a746bc04439be5a2 (diff) | |
| download | yosys-cdb566b2d6a998ccaf5406f584e3ec810973dff9.tar.gz yosys-cdb566b2d6a998ccaf5406f584e3ec810973dff9.tar.bz2 yosys-cdb566b2d6a998ccaf5406f584e3ec810973dff9.zip | |
Merge pull request #1494 from whitequark/write_verilog-extmem
write_verilog: add -extmem option, to write split memory init files
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions