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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-04-18 09:09:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-04-18 09:09:36 +0200 |
| commit | d23260d381a1b58ff7f0a0ce65e1884e2ceaa05d (patch) | |
| tree | 1eb6aa16dbd750800dd4a10f68336d105da0644c /frontends/verilog | |
| parent | 36b5caf8217d4ca57b2c53cd76da5f1ace74a20f (diff) | |
| parent | 57bc29c64a546fc1dc9a14f0d19a1e30fb5948f0 (diff) | |
| download | yosys-d23260d381a1b58ff7f0a0ce65e1884e2ceaa05d.tar.gz yosys-d23260d381a1b58ff7f0a0ce65e1884e2ceaa05d.tar.bz2 yosys-d23260d381a1b58ff7f0a0ce65e1884e2ceaa05d.zip | |
Merge pull request #3282 from nakengelhardt/verific_loop_rams
verific: allow memories to be inferred in loops
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions