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| author | Archie <ac11018@ic.ac.uk> | 2022-10-02 21:59:46 +0200 |
|---|---|---|
| committer | Archie <ac11018@ic.ac.uk> | 2022-10-02 22:05:51 +0200 |
| commit | d29606532a15ae8e0c8d6c3591ccb36652d7339b (patch) | |
| tree | c17d7f68fdc426e8c47b0eb261be0313915dbccf /frontends/verilog | |
| parent | 15a0697c70e14d6277e26f6fa21898be5a8f6ff8 (diff) | |
| download | yosys-d29606532a15ae8e0c8d6c3591ccb36652d7339b.tar.gz yosys-d29606532a15ae8e0c8d6c3591ccb36652d7339b.tar.bz2 yosys-d29606532a15ae8e0c8d6c3591ccb36652d7339b.zip | |
Changing error reason string to be based on lut input plane limit constant.
Diffstat (limited to 'frontends/verilog')
0 files changed, 0 insertions, 0 deletions