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| author | Stefan Biereigel <stefan.biereigel@cern.ch> | 2019-05-23 13:42:30 +0200 |
|---|---|---|
| committer | Stefan Biereigel <stefan.biereigel@cern.ch> | 2019-05-23 13:57:27 +0200 |
| commit | fd003e0e975be3c7f357fb151fd1c83a8ea9b0ae (patch) | |
| tree | e7b097e7b162f674ced32e2ce7c29239b0b8a59d /frontends/verilog | |
| parent | 075a48d3fa69324d5b2700779a686fa46a69adb2 (diff) | |
| download | yosys-fd003e0e975be3c7f357fb151fd1c83a8ea9b0ae.tar.gz yosys-fd003e0e975be3c7f357fb151fd1c83a8ea9b0ae.tar.bz2 yosys-fd003e0e975be3c7f357fb151fd1c83a8ea9b0ae.zip | |
fix indentation across files
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8800705ac..8244a8f44 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -486,10 +486,10 @@ wire_type_token: TOK_WIRE { } | TOK_WOR { - astbuf3->is_wor = true; + astbuf3->is_wor = true; } | TOK_WAND { - astbuf3->is_wand = true; + astbuf3->is_wand = true; } | TOK_REG { astbuf3->is_reg = true; |