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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:23:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:23:22 -0700 |
| commit | fd3b033903bf005c4308923ccb34ab269d55dd3e (patch) | |
| tree | bdb846f228a6517612fab5b7f19a642c91fd093d /frontends/verilog | |
| parent | 25e0f0c3765060b7ce25a0c58bc926b90dba304d (diff) | |
| parent | 3ec28ec53a4350d041cd24a4fa9b03e985d20d95 (diff) | |
| download | yosys-fd3b033903bf005c4308923ccb34ab269d55dd3e.tar.gz yosys-fd3b033903bf005c4308923ccb34ab269d55dd3e.tar.bz2 yosys-fd3b033903bf005c4308923ccb34ab269d55dd3e.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 10 | ||||
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 |
2 files changed, 4 insertions, 8 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 4bf5b1cf5..49281f7e7 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -85,10 +85,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le digits.push_back(10 + *str - 'A'); else if (*str == 'x' || *str == 'X') digits.push_back(0xf0); - else if (*str == 'z' || *str == 'Z') + else if (*str == 'z' || *str == 'Z' || *str == '?') digits.push_back(0xf1); - else if (*str == '?') - digits.push_back(0xf2); str++; } @@ -112,8 +110,6 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx); else if (*it == 0xf1) data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz); - else if (*it == 0xf2) - data.push_back(RTLIL::Sa); else data.push_back((*it & bitmask) ? State::S1 : State::S0); } @@ -199,13 +195,13 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn if (str == endptr) len_in_bits = -1; - // The "<bits>'s?[bodhBODH]<digits>" syntax + // The "<bits>'[sS]?[bodhBODH]<digits>" syntax if (*endptr == '\'') { std::vector<RTLIL::State> data; bool is_signed = false; bool is_unsized = len_in_bits < 0; - if (*(endptr+1) == 's') { + if (*(endptr+1) == 's' || *(endptr+1) == 'S') { is_signed = true; endptr++; } diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 57e55b1f4..4acfb414d 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -239,7 +239,7 @@ YOSYS_NAMESPACE_END return TOK_CONSTVAL; } -[0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ { +[0-9]*[ \t]*\'[sS]?[bodhBODH]?[ \t\r\n]*[0-9a-fA-FzxZX?_]+ { frontend_verilog_yylval.string = new std::string(yytext); return TOK_CONSTVAL; } |