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| author | dh73 <dh73_fpga@qq.com> | 2017-11-08 20:24:01 -0600 |
|---|---|---|
| committer | dh73 <dh73_fpga@qq.com> | 2017-11-08 20:24:01 -0600 |
| commit | cf8cc50bf51c2fa36a3189e131a7e7fe0807ae8f (patch) | |
| tree | 456b6aae2215835e602851eafc3b52bb6bb6f3de /frontends/vhdl2verilog/Makefile.inc | |
| parent | 1fc061d90c45166f87d92f76b6fae1ec517be72f (diff) | |
| parent | 9ae25039fb6e28db639372d67c1b72c4170feaa3 (diff) | |
| download | yosys-cf8cc50bf51c2fa36a3189e131a7e7fe0807ae8f.tar.gz yosys-cf8cc50bf51c2fa36a3189e131a7e7fe0807ae8f.tar.bz2 yosys-cf8cc50bf51c2fa36a3189e131a7e7fe0807ae8f.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'frontends/vhdl2verilog/Makefile.inc')
| -rw-r--r-- | frontends/vhdl2verilog/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/frontends/vhdl2verilog/Makefile.inc b/frontends/vhdl2verilog/Makefile.inc deleted file mode 100644 index 003d89c4a..000000000 --- a/frontends/vhdl2verilog/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -OBJS += frontends/vhdl2verilog/vhdl2verilog.o |