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| author | Siesh1oo <siesh1oo@siesh1oo.no> | 2014-03-10 14:36:07 +0100 |
|---|---|---|
| committer | Siesh1oo <siesh1oo@siesh1oo.no> | 2014-03-10 14:36:07 +0100 |
| commit | 8111938e962b60294e51d5f0d10b6d1855bc1b91 (patch) | |
| tree | d1696423105b392520e8f77327ae4410222a1354 /frontends/vhdl2verilog/vhdl2verilog.cc | |
| parent | 40e0b79495195eaa2bc6bf32e8d52a5aa956a2b4 (diff) | |
| download | yosys-8111938e962b60294e51d5f0d10b6d1855bc1b91.tar.gz yosys-8111938e962b60294e51d5f0d10b6d1855bc1b91.tar.bz2 yosys-8111938e962b60294e51d5f0d10b6d1855bc1b91.zip | |
- kernel/log.h: add rusage()-based fallback for systems without clock_gettime().
Diffstat (limited to 'frontends/vhdl2verilog/vhdl2verilog.cc')
0 files changed, 0 insertions, 0 deletions