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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
| commit | ab11f2aa701f4ff7a8df98d2a4158ea1f661a205 (patch) | |
| tree | d2c8e2b82b7cca57127bd9dd54d3eb40386a88f7 /frontends/vhdl2verilog/vhdl2verilog.cc | |
| parent | d90c1e952256dc00d070863835e061d73e4bc6b3 (diff) | |
| parent | 7311be4028a9caad5a0fac1a3433220b4233ef84 (diff) | |
| download | yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.gz yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.bz2 yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'frontends/vhdl2verilog/vhdl2verilog.cc')
| -rw-r--r-- | frontends/vhdl2verilog/vhdl2verilog.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc index 80bf243f0..6f9c0e3f5 100644 --- a/frontends/vhdl2verilog/vhdl2verilog.cc +++ b/frontends/vhdl2verilog/vhdl2verilog.cc @@ -74,7 +74,7 @@ struct Vhdl2verilogPass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing VHDL2VERILOG (importing VHDL designs using vhdl2verilog).\n"); + log_header(design, "Executing VHDL2VERILOG (importing VHDL designs using vhdl2verilog).\n"); log_push(); std::string out_file, top_entity; @@ -173,7 +173,7 @@ struct Vhdl2verilogPass : public Pass { Frontend::frontend_call(design, &ff, stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()), "verilog"); } - log_header("Removing temp directory `%s':\n", tempdir_name.c_str()); + log_header(design, "Removing temp directory `%s':\n", tempdir_name.c_str()); remove_directory(tempdir_name); log_pop(); } |