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| author | Clifford Wolf <clifford@clifford.at> | 2017-01-31 10:15:04 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-01-31 10:15:04 +0100 |
| commit | 7481ba4750b5c65c9dc2c64ae29027f328f25bfe (patch) | |
| tree | 0c3aabbfcf22238a10077f8f8121a1bdc36a87c0 /frontends/vhdl2verilog | |
| parent | 18ea65ef04889e5016f007d3a034c8c49709cdb6 (diff) | |
| download | yosys-7481ba4750b5c65c9dc2c64ae29027f328f25bfe.tar.gz yosys-7481ba4750b5c65c9dc2c64ae29027f328f25bfe.tar.bz2 yosys-7481ba4750b5c65c9dc2c64ae29027f328f25bfe.zip | |
Improve opt_rmdff support for $dlatch cells
Diffstat (limited to 'frontends/vhdl2verilog')
0 files changed, 0 insertions, 0 deletions