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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-13 14:08:31 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-13 14:08:31 -0800 |
| commit | 06cf0555ee0b28948295d8c9aedd2583c16ecc6a (patch) | |
| tree | 1c1389fb4c874b7edaa865bfc99d17887440a721 /frontends | |
| parent | 87f059adf7c075cc5dfe2e01b674fffa567db425 (diff) | |
| parent | 807b3c769733b8cf07f5b14674df41bd2788e09d (diff) | |
| download | yosys-06cf0555ee0b28948295d8c9aedd2583c16ecc6a.tar.gz yosys-06cf0555ee0b28948295d8c9aedd2583c16ecc6a.tar.bz2 yosys-06cf0555ee0b28948295d8c9aedd2583c16ecc6a.zip | |
Merge https://github.com/YosysHQ/yosys into xaig
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 9531dd356..e66625228 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -942,16 +942,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node case AST_CONSTANT: + case AST_REALVALUE: { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); - is_signed = sign_hint; - return RTLIL::SigSpec(bitsAsConst()); - } - case AST_REALVALUE: - { + if (type == AST_CONSTANT) + return RTLIL::SigSpec(bitsAsConst()); + RTLIL::SigSpec sig = realAsConst(width_hint); log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig)); return sig; |