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authorMiodrag Milanović <mmicko@gmail.com>2021-01-21 16:56:19 +0100
committerGitHub <noreply@github.com>2021-01-21 16:56:19 +0100
commit1f88a3de74eae3896e39795fd5a12d885ab29a93 (patch)
tree2d887c1512458456391bb6c098f2dc2eba46db90 /frontends
parent699a98b265a41b0565637323f929e6cb1f8837e0 (diff)
parent1096b969efb24dc28b501585f23ceb242d781745 (diff)
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Merge pull request #2553 from zachjs/rand-const-modifiers
Allow combination of rand and const modifiers
Diffstat (limited to 'frontends')
-rw-r--r--frontends/verilog/verilog_parser.y12
1 files changed, 10 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2886db0e5..8bd58d24c 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -651,8 +651,16 @@ wire_type_signedness:
%empty;
wire_type_const_rand:
- TOK_CONST { current_wire_const = true; } |
- TOK_RAND { current_wire_rand = true; } |
+ TOK_RAND TOK_CONST {
+ current_wire_rand = true;
+ current_wire_const = true;
+ } |
+ TOK_CONST {
+ current_wire_const = true;
+ } |
+ TOK_RAND {
+ current_wire_rand = true;
+ } |
%empty;
opt_wire_type_token: