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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-07 16:41:27 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-07 16:41:27 +0200 |
| commit | 2dc33337346ea53a654af3d80bdf056c7ccfa43c (patch) | |
| tree | 85bb47c1f10a6a82b79472ace19da4258ff5f295 /frontends | |
| parent | 312ee00c9e279a91f336acef26dd064c25f42ed5 (diff) | |
| download | yosys-2dc33337346ea53a654af3d80bdf056c7ccfa43c.tar.gz yosys-2dc33337346ea53a654af3d80bdf056c7ccfa43c.tar.bz2 yosys-2dc33337346ea53a654af3d80bdf056c7ccfa43c.zip | |
Also allow "module foobar(input foo, output bar, ...);" syntax
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/parser.y | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 95d7f3935..f619d3c2b 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -247,8 +247,7 @@ single_module_para: }; module_args_opt: - '(' ')' | /* empty */ | '(' module_args optional_comma ')' | - '(' '.' '.' '.' ')' { do_not_require_port_stubs = true; }; + '(' ')' | /* empty */ | '(' module_args optional_comma ')'; module_args: module_arg | module_args ',' module_arg; @@ -297,7 +296,10 @@ module_arg: ast_stack.back()->children.push_back(node); append_attr(node, $1); delete $4; - } module_arg_opt_assignment; + } module_arg_opt_assignment | + '.' '.' '.' { + do_not_require_port_stubs = true; + }; wire_type: { |