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| author | whitequark <whitequark@whitequark.org> | 2021-03-01 22:46:07 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-01 22:46:07 -0800 |
| commit | 375af199ef4df45ccf02c66e0171b4282c6cf1eb (patch) | |
| tree | 18e54f4b88b8cb4639da0a1d688d07200bacec3b /frontends | |
| parent | 0e0f84299a4ae4d0a312c33039378e1ebb20709d (diff) | |
| parent | 10a6bc9b81d1c2236e80a608778c904aebe54c28 (diff) | |
| download | yosys-375af199ef4df45ccf02c66e0171b4282c6cf1eb.tar.gz yosys-375af199ef4df45ccf02c66e0171b4282c6cf1eb.tar.bz2 yosys-375af199ef4df45ccf02c66e0171b4282c6cf1eb.zip | |
Merge pull request #2620 from zachjs/port-int-types
verilog: fix sizing of ports with int types in module headers
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 476ee68ad..bcba9b76a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -546,8 +546,9 @@ module_arg: node->str = *$4; SET_AST_NODE_LOC(node, @4, @4); node->port_id = ++port_counter; - if ($3 != NULL) - node->children.push_back($3); + AstNode *range = checkRange(node, $3); + if (range != NULL) + node->children.push_back(range); if (!node->is_input && !node->is_output) frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str()); if (node->is_reg && node->is_input && !node->is_output && !sv_mode) |