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author | Clifford Wolf <clifford@clifford.at> | 2019-10-21 13:35:31 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-10-21 13:35:56 +0200 |
commit | 5025aab8c9b47e2a201f7ffd494475882db92398 (patch) | |
tree | d0ffd392074e44c874b775a6c3849d1c2c1473fb /frontends | |
parent | 4033ff8c2ed2d312b0dc54940502c6ff9c34ebe7 (diff) | |
download | yosys-5025aab8c9b47e2a201f7ffd494475882db92398.tar.gz yosys-5025aab8c9b47e2a201f7ffd494475882db92398.tar.bz2 yosys-5025aab8c9b47e2a201f7ffd494475882db92398.zip |
Add "verilog_defines -list" and "verilog_defines -reset"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends')
-rw-r--r-- | frontends/verilog/verilog_frontend.cc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 0e2bead6f..058d750c3 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -553,6 +553,12 @@ struct VerilogDefines : public Pass { log(" -Uname[=definition]\n"); log(" undefine the preprocessor symbol 'name'\n"); log("\n"); + log(" -reset\n"); + log(" clear list of defined preprocessor symbols\n"); + log("\n"); + log(" -list\n"); + log(" list currently defined preprocessor symbols\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -588,6 +594,16 @@ struct VerilogDefines : public Pass { design->verilog_defines.erase(name); continue; } + if (arg == "-reset") { + design->verilog_defines.clear(); + continue; + } + if (arg == "-list") { + for (auto &it : design->verilog_defines) { + log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str()); + } + continue; + } break; } |