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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 15:31:19 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 15:31:19 +0200 |
| commit | 55521c085ae1ec735d3cffb80a9880b3cb3e8bca (patch) | |
| tree | 3f35dae3b57897aab8a0c92fdcfd1a2a10cb4226 /frontends | |
| parent | 0598bc8708d942a0e533ddeba6a4f7b5effe7f39 (diff) | |
| download | yosys-55521c085ae1ec735d3cffb80a9880b3cb3e8bca.tar.gz yosys-55521c085ae1ec735d3cffb80a9880b3cb3e8bca.tar.bz2 yosys-55521c085ae1ec735d3cffb80a9880b3cb3e8bca.zip | |
Fixed RTLIL code generator for part select of parameter
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 9e1866832..ca61cb39b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -912,7 +912,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) children[0]->children[1]->clone() : children[0]->children[0]->clone()); fake_ast->children[0]->delete_children(); RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width, - fake_ast->children[0]->genRTLIL(), !wire->upto ? fake_ast->children[1]->genRTLIL() : + fake_ast->children[0]->genRTLIL(), !id2ast->range_swapped ? fake_ast->children[1]->genRTLIL() : current_module->Sub(NEW_ID, RTLIL::SigSpec(wire->width - width), fake_ast->children[1]->genRTLIL())); delete left_at_zero_ast; delete right_at_zero_ast; @@ -924,7 +924,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) str.c_str(), filename.c_str(), linenum); chunk.width = children[0]->range_left - children[0]->range_right + 1; chunk.offset = children[0]->range_right - id2ast->range_right; - if (wire->upto) + if (id2ast->range_swapped) chunk.offset = wire->width - (chunk.offset + chunk.width); } } |