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author | Miodrag Milanovic <mmicko@gmail.com> | 2023-01-17 12:58:08 +0100 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2023-01-17 12:58:08 +0100 |
commit | 6574553189fb6ccb5d00a0c043671a625672b3d3 (patch) | |
tree | 57e3212ee75493d9f4939c9f9029b95880367a76 /frontends | |
parent | 956c4e485a9463863f60c4dd03372db3fa8332a4 (diff) | |
download | yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.tar.gz yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.tar.bz2 yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.zip |
Fixes for some of clang scan-build detected issues
Diffstat (limited to 'frontends')
-rw-r--r-- | frontends/ast/ast.cc | 3 | ||||
-rw-r--r-- | frontends/ast/simplify.cc | 3 | ||||
-rw-r--r-- | frontends/verific/verific.cc | 10 | ||||
-rw-r--r-- | frontends/verific/verificsva.cc | 4 |
4 files changed, 11 insertions, 9 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 6097f02f5..982943d1b 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1649,7 +1649,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr AstNode *new_ast = NULL; std::string modname = derive_common(design, parameters, &new_ast, quiet); - if (!design->has(modname)) { + if (!design->has(modname) && new_ast) { new_ast->str = modname; process_module(design, new_ast, false, NULL, quiet); design->module(modname)->check(); @@ -1699,6 +1699,7 @@ std::string AST::derived_module_name(std::string stripped_name, const std::vecto std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet) { std::string stripped_name = name.str(); + (*new_ast_out) = nullptr; if (stripped_name.compare(0, 9, "$abstract") == 0) stripped_name = stripped_name.substr(9); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index da7933d2f..71a26983b 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -4705,8 +4705,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg children_flags |= AstNode::MEM2REG_FL_ASYNC; proc_flags_p = new dict<AstNode*, uint32_t>; } - - if (type == AST_INITIAL) { + else if (type == AST_INITIAL) { children_flags |= AstNode::MEM2REG_FL_INIT; proc_flags_p = new dict<AstNode*, uint32_t>; } diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a93d79c80..8898c4597 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2317,8 +2317,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin const char *lib_name = (prefix) ? prefix->GetName() : 0 ; if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; } - veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0; - top = veri_module->GetName(); + if (lib && module_name) + top = lib->GetModule(module_name->GetName(), 1)->GetName(); } } @@ -2344,6 +2344,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin int i; FOREACH_ARRAY_ITEM(netlists, i, nl) { + if (!nl) continue; if (!top.empty() && nl->CellBaseName() != top) continue; nl->AddAtt(new Att(" \\top", NULL)); @@ -3297,8 +3298,8 @@ struct VerificPass : public Pass { const char *lib_name = (prefix) ? prefix->GetName() : 0 ; if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; } - veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0; - top_mod_names.insert(veri_module->GetName()); + if (lib && module_name) + top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); } } else { log("Adding Verilog module '%s' to elaboration queue.\n", name); @@ -3333,6 +3334,7 @@ struct VerificPass : public Pass { int i; FOREACH_ARRAY_ITEM(netlists, i, nl) { + if (!nl) continue; if (!top_mod_names.count(nl->CellBaseName())) continue; nl->AddAtt(new Att(" \\top", NULL)); diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 12bac2a3d..986a98643 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1777,7 +1777,7 @@ struct VerificSvaImporter if (mode_assert) c = module->addLive(root_name, sig_a_q, sig_en_q); if (mode_assume) c = module->addFair(root_name, sig_a_q, sig_en_q); - importer->import_attributes(c->attributes, root); + if (c) importer->import_attributes(c->attributes, root); return; } @@ -1822,7 +1822,7 @@ struct VerificSvaImporter if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q); if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q); - importer->import_attributes(c->attributes, root); + if (c) importer->import_attributes(c->attributes, root); } } catch (ParserErrorException) |