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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-28 23:48:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-28 23:48:17 -0700 |
| commit | 79b6edb6397c530a7304eb4334f95324a4208aba (patch) | |
| tree | 3a3c3fd9511c2dbe31e0fcbf71771596eeb6a2c3 /frontends | |
| parent | cfa6dd61ef79fb16abd83164b1e013c0a5a2a63a (diff) | |
| download | yosys-79b6edb6397c530a7304eb4334f95324a4208aba.tar.gz yosys-79b6edb6397c530a7304eb4334f95324a4208aba.tar.bz2 yosys-79b6edb6397c530a7304eb4334f95324a4208aba.zip | |
Big rework; flop info now mostly in cells_sim.v
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7a467b91e..439311230 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -740,7 +740,7 @@ void AigerReader::post_process() bool is_flop = false; if (seen_boxes.insert(cell->type).second) { - if (box_module->attributes.count("\\abc_flop")) { + if (box_module->attributes.count("\\abc9_flop")) { log_assert(flop_count < flopNum); flops.insert(cell->type); is_flop = true; @@ -811,12 +811,18 @@ void AigerReader::post_process() } rhs.append(wire); } - - if (!is_flop || port_name != "\\$pastQ") - cell->setPort(port_name, rhs); + cell->setPort(port_name, rhs); } if (is_flop) { + Wire* port = box_module->wire("\\$currQ"); + log_assert(port); + log_assert(co_count < outputs.size()); + Wire *wire = outputs[co_count++]; + log_assert(wire); + log_assert(wire->port_output); + wire->port_output = false; + RTLIL::Wire *d = outputs[outputs.size() - flopNum + flop_count]; log_assert(d); log_assert(d->port_output); @@ -827,9 +833,10 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; + auto ff = module->addCell(NEW_ID, "$__ABC_FF_"); + ff->setPort("\\D", d); + ff->setPort("\\Q", q); flop_count++; - module->connect(q, d); - cell->set_bool_attribute("\\abc_flop"); continue; } } |