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| author | clairexen <claire@symbioticeda.com> | 2020-07-09 18:39:30 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-09 18:39:30 +0200 |
| commit | 802671b22edbedda593d4c256423975786c581a3 (patch) | |
| tree | 64e77efb358aefd438d4cf1ed87ab0852a8519e4 /frontends | |
| parent | 03e28f7ab43116cd4f7fed0e37647637a4d8eda0 (diff) | |
| parent | b422f2e4d0b8d5bfa97913d6b9dee488b59fc405 (diff) | |
| download | yosys-802671b22edbedda593d4c256423975786c581a3.tar.gz yosys-802671b22edbedda593d4c256423975786c581a3.tar.bz2 yosys-802671b22edbedda593d4c256423975786c581a3.zip | |
Merge pull request #2244 from antmicro/logic
Add logic type support to parameters
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 656910c0c..dfdb11cf0 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1337,8 +1337,6 @@ param_signed: param_integer: TOK_INTEGER { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Internal error in param_integer - should not happen?"); astbuf1->children.push_back(new AstNode(AST_RANGE)); astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true)); astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true)); @@ -1347,16 +1345,19 @@ param_integer: param_real: TOK_REAL { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real."); astbuf1->children.push_back(new AstNode(AST_REALVALUE)); } +param_logic: + TOK_LOGIC { + // SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned + astbuf1->is_signed = false; + astbuf1->is_logic = true; + } + param_range: range { if ($1 != NULL) { - if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("integer/real parameters should not have a range."); astbuf1->children.push_back($1); } }; @@ -1365,8 +1366,10 @@ param_integer_type: param_integer param_signed param_range_type: type_vec param_signed param_range param_implicit_type: param_signed param_range +param_integer_vector_type: param_logic param_signed param_range + param_type: - param_integer_type | param_real | param_range_type | param_implicit_type | + param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type | hierarchical_type_id { astbuf1->is_custom_type = true; astbuf1->children.push_back(new AstNode(AST_WIRETYPE)); |