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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 15:36:07 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 15:36:07 -0700 |
commit | ba629e6a288e0445c648623c2aeae194d41752fd (patch) | |
tree | 8329bd146164d79c39b9aff75f0e42a4ce7459db /frontends | |
parent | 3459d283492769263e73a0e35d0e5d253c0bbec7 (diff) | |
parent | 8c1a98249457b790895aee76115ddd40ec891555 (diff) | |
download | yosys-ba629e6a288e0445c648623c2aeae194d41752fd.tar.gz yosys-ba629e6a288e0445c648623c2aeae194d41752fd.tar.bz2 yosys-ba629e6a288e0445c648623c2aeae194d41752fd.zip |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'frontends')
-rw-r--r-- | frontends/ast/ast.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 82283fb5b..a3a78e414 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1099,6 +1099,13 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast ignoreThisSignalsInInitial = RTLIL::SigSpec(); } + else { + for (auto &attr : ast->attributes) { + if (attr.second->type != AST_CONSTANT) + continue; + current_module->attributes[attr.first] = attr.second->asAttrConst(); + } + } if (ast->type == AST_INTERFACE) current_module->set_bool_attribute("\\is_interface"); |