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| author | Jannis Harder <me@jix.one> | 2023-04-24 16:08:48 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-24 16:08:48 +0200 |
| commit | cee3cb31b98e3b67af3165969c8cfc0616c37e19 (patch) | |
| tree | f146d725bdaf0262f04bcd6092a34abbd127f3ad /frontends | |
| parent | 51dd0290241c521f5498f71f4fd4fb0598d83a76 (diff) | |
| parent | 985f4926b77aef98a2639624a44e155b2233c3ad (diff) | |
| download | yosys-cee3cb31b98e3b67af3165969c8cfc0616c37e19.tar.gz yosys-cee3cb31b98e3b67af3165969c8cfc0616c37e19.tar.bz2 yosys-cee3cb31b98e3b67af3165969c8cfc0616c37e19.zip | |
verilog: Fix const eval of unbased unsized constants
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 5a2ade04a..91001c70d 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -847,7 +847,7 @@ RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed) bits.resize(width); if (width >= 0 && width > int(bits.size())) { RTLIL::State extbit = RTLIL::State::S0; - if (is_signed && !bits.empty()) + if ((is_signed || is_unsized) && !bits.empty()) extbit = bits.back(); while (width > int(bits.size())) bits.push_back(extbit); |