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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 13:14:23 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-15 13:14:23 +0200 |
| commit | d71529baa1deb224ab520b2431b2c1a176170054 (patch) | |
| tree | 636bedf67d6baf44a2910e188caad2c8613b7563 /frontends | |
| parent | 1dd156f5167d9949eccb7abcbc65d9bc74f49ee8 (diff) | |
| parent | 8b7580b0a152ec937abb1510abf5f2d7cd3b7acb (diff) | |
| download | yosys-d71529baa1deb224ab520b2431b2c1a176170054.tar.gz yosys-d71529baa1deb224ab520b2431b2c1a176170054.tar.bz2 yosys-d71529baa1deb224ab520b2431b2c1a176170054.zip | |
Merge pull request #562 from udif/pr_fix_illegal_port_decl
Detect illegal port declaration, e.g input/output/inout keyword must …
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e803d8072..72a501d11 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -376,9 +376,10 @@ wire_type: }; wire_type_token_list: - wire_type_token | wire_type_token_list wire_type_token; + wire_type_token | wire_type_token_list wire_type_token | + wire_type_token_io ; -wire_type_token: +wire_type_token_io: TOK_INPUT { astbuf3->is_input = true; } | @@ -388,7 +389,9 @@ wire_type_token: TOK_INOUT { astbuf3->is_input = true; astbuf3->is_output = true; - } | + }; + +wire_type_token: TOK_WIRE { } | TOK_REG { |