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| author | Peter Gadfort <peter.gadfort@gmail.com> | 2023-01-02 12:46:41 -0500 |
|---|---|---|
| committer | Peter Gadfort <peter.gadfort@gmail.com> | 2023-01-02 12:46:41 -0500 |
| commit | 7971154e727cc4d7c4b8c62ad43a28645bb66795 (patch) | |
| tree | ea4632f116b272bc15940cc59f45a73eef008566 /guidelines/Checklists | |
| parent | 58cca9592d64178a097c6345a576b1df022cd50c (diff) | |
| parent | 583ab81670847bc0084708bab04c64cb43bc3a51 (diff) | |
| download | yosys-7971154e727cc4d7c4b8c62ad43a28645bb66795.tar.gz yosys-7971154e727cc4d7c4b8c62ad43a28645bb66795.tar.bz2 yosys-7971154e727cc4d7c4b8c62ad43a28645bb66795.zip | |
Merge branch 'master' into stat-json-area
Diffstat (limited to 'guidelines/Checklists')
| -rw-r--r-- | guidelines/Checklists | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/guidelines/Checklists b/guidelines/Checklists index cc61c7876..51756cfd7 100644 --- a/guidelines/Checklists +++ b/guidelines/Checklists @@ -11,7 +11,7 @@ Things to do right away: Things to do after finalizing the cell interface: - Add support to kernel/satgen.h for the new cell type - - Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom) + - Add to docs/source/CHAPTER_CellLib.rst (or just add a fixme to the bottom) - Maybe add support to the Verilog backend for dumping such cells as expression @@ -29,11 +29,9 @@ Update the CHANGELOG file: Update and check documentation: cd ~yosys - make update-manual - make manual - - sanity check the figures in the appnotes and presentation + make docs + - sanity check the figures in docs/images - if there are any odd things -> investigate - - make cosmetic changes to the .tex files if necessary cd ~yosys vi README guidelines/* @@ -108,13 +106,11 @@ Release: Updating the website: cd ~yosys - make manual make install - - update pdf files on the website - cd ~yosys-web - make update_cmd make update_show git commit -am update make push + + - Read the Docs updates handled by Jenkins on source change |