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| author | Alastair M. Robinson <robinsonb5@gmail.com> | 2022-05-10 18:48:54 +0100 |
|---|---|---|
| committer | Alastair M. Robinson <robinsonb5@gmail.com> | 2022-05-10 18:48:54 +0100 |
| commit | 83dbea1689bd0efd5645cf75b40aa4cec430fc90 (patch) | |
| tree | b33a13e71701332746a1a356826e9999740456d0 /kernel/cellaigs.h | |
| parent | c862b1dbfbb3a8e1ec90c483a8364550b3fe840c (diff) | |
| download | yosys-83dbea1689bd0efd5645cf75b40aa4cec430fc90.tar.gz yosys-83dbea1689bd0efd5645cf75b40aa4cec430fc90.tar.bz2 yosys-83dbea1689bd0efd5645cf75b40aa4cec430fc90.zip | |
Now calls Tcl_Init after creating the interp, fixes clock format.
Diffstat (limited to 'kernel/cellaigs.h')
0 files changed, 0 insertions, 0 deletions