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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-19 13:04:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-19 13:04:06 +0200 |
| commit | 1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9 (patch) | |
| tree | 7b7830c5da434964fd40792c393c45a31b8ad080 /kernel/celledges.cc | |
| parent | f20be90436b32e853d68c7e102a65d43f3843d91 (diff) | |
| parent | 3edb0abed88565447d5193f78261400655aa843a (diff) | |
| download | yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.tar.gz yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.tar.bz2 yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
Diffstat (limited to 'kernel/celledges.cc')
| -rw-r--r-- | kernel/celledges.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 7a324a06e..d0bb99e83 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -41,7 +41,7 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -71,7 +71,7 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -87,7 +87,7 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int a_width = GetSize(cell->getPort(A)); @@ -114,7 +114,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), Y = ID(Y); + IdString A = ID::A, Y = ID::Y; int a_width = GetSize(cell->getPort(A)); @@ -124,7 +124,7 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), Y = ID(Y); + IdString A = ID::A, B = ID::B, Y = ID::Y; int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); @@ -138,7 +138,7 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID(A), B = ID(B), S = ID(S), Y = ID(Y); + IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; int a_width = GetSize(cell->getPort(A)); int b_width = GetSize(cell->getPort(B)); |