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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-15 10:22:23 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-15 10:22:23 +0100 |
| commit | 89f009d17187690fe0446fd95a1f623516a33f3d (patch) | |
| tree | 1f8329839c3c25536fc57faa1e9f03c94e0b7d9a /kernel/celltypes.h | |
| parent | 3377a04bf26b9310017a71b2df587bad661e0da2 (diff) | |
| download | yosys-89f009d17187690fe0446fd95a1f623516a33f3d.tar.gz yosys-89f009d17187690fe0446fd95a1f623516a33f3d.tar.bz2 yosys-89f009d17187690fe0446fd95a1f623516a33f3d.zip | |
Added additional functionality and cleanups in sigtools.h and celltypes.h
Diffstat (limited to 'kernel/celltypes.h')
| -rw-r--r-- | kernel/celltypes.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 6273e926a..bf5ef4b38 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -29,6 +29,15 @@ struct CellTypes std::set<std::string> cell_types; std::vector<const RTLIL::Design*> designs; + CellTypes() + { + } + + CellTypes(const RTLIL::Design *design) + { + setup(design); + } + void setup(const RTLIL::Design *design = NULL) { if (design) |