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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-01-24 16:02:29 +0100 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-01-28 23:34:41 +0100 |
commit | 93508d58dafbbffcedffa70b21a197b6fca8bb30 (patch) | |
tree | 4f4bed22749559a1938457015ff875891fd7a40a /kernel/consteval.h | |
parent | db33b1e535f5ee93dba9ee1cc181b91c482a4dee (diff) | |
download | yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.tar.gz yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.tar.bz2 yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.zip |
Add $bmux and $demux cells.
Diffstat (limited to 'kernel/consteval.h')
-rw-r--r-- | kernel/consteval.h | 35 |
1 files changed, 33 insertions, 2 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h index 3edfc490c..642eb42b2 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -135,8 +135,6 @@ struct ConstEval if (cell->hasPort(ID::S)) { sig_s = cell->getPort(ID::S); - if (!eval(sig_s, undef, cell)) - return false; } if (cell->hasPort(ID::A)) @@ -151,6 +149,9 @@ struct ConstEval int count_maybe_set_s_bits = 0; int count_set_s_bits = 0; + if (!eval(sig_s, undef, cell)) + return false; + for (int i = 0; i < sig_s.size(); i++) { RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0); @@ -198,6 +199,36 @@ struct ConstEval else set(sig_y, y_values.front()); } + else if (cell->type == ID($bmux)) + { + if (!eval(sig_s, undef, cell)) + return false; + + if (sig_s.is_fully_def()) { + int sel = sig_s.as_int(); + int width = GetSize(sig_y); + SigSpec res = sig_a.extract(sel * width, width); + if (!eval(res, undef, cell)) + return false; + set(sig_y, res.as_const()); + } else { + if (!eval(sig_a, undef, cell)) + return false; + set(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const())); + } + } + else if (cell->type == ID($demux)) + { + if (!eval(sig_a, undef, cell)) + return false; + if (sig_a.is_fully_zero()) { + set(sig_y, Const(0, GetSize(sig_y))); + } else { + if (!eval(sig_s, undef, cell)) + return false; + set(sig_y, const_demux(sig_a.as_const(), sig_s.as_const())); + } + } else if (cell->type == ID($fa)) { RTLIL::SigSpec sig_c = cell->getPort(ID::C); |