aboutsummaryrefslogtreecommitdiffstats
path: root/kernel/macc.h
diff options
context:
space:
mode:
authorEddie Hung <eddie@fpgeh.com>2019-08-15 06:48:40 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-15 06:48:40 -0700
commit91f6cdfef6af69b7fe9203ee4d501ab6e6f1a830 (patch)
treeb749ff51dec39f145cc25a1df262de7412f5c45a /kernel/macc.h
parent1551e14d2d688982f22f416a55a3212796a82421 (diff)
parent704686774e28b9b602874264df2c0f96841be05e (diff)
downloadyosys-91f6cdfef6af69b7fe9203ee4d501ab6e6f1a830.tar.gz
yosys-91f6cdfef6af69b7fe9203ee4d501ab6e6f1a830.tar.bz2
yosys-91f6cdfef6af69b7fe9203ee4d501ab6e6f1a830.zip
Merge remote-tracking branch 'origin/master' into eddie/fix_1284_again
Diffstat (limited to 'kernel/macc.h')
-rw-r--r--kernel/macc.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/kernel/macc.h b/kernel/macc.h
index c7595ebc1..e07e7e01a 100644
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -99,16 +99,16 @@ struct Macc
void from_cell(RTLIL::Cell *cell)
{
- RTLIL::SigSpec port_a = cell->getPort("\\A");
+ RTLIL::SigSpec port_a = cell->getPort(ID(A));
ports.clear();
- bit_ports = cell->getPort("\\B");
+ bit_ports = cell->getPort(ID(B));
- std::vector<RTLIL::State> config_bits = cell->getParam("\\CONFIG").bits;
+ std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits;
int config_cursor = 0;
#ifndef NDEBUG
- int config_width = cell->getParam("\\CONFIG_WIDTH").as_int();
+ int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int();
log_assert(GetSize(config_bits) >= config_width);
#endif
@@ -191,12 +191,12 @@ struct Macc
port_a.append(port.in_b);
}
- cell->setPort("\\A", port_a);
- cell->setPort("\\B", bit_ports);
- cell->setParam("\\CONFIG", config_bits);
- cell->setParam("\\CONFIG_WIDTH", GetSize(config_bits));
- cell->setParam("\\A_WIDTH", GetSize(port_a));
- cell->setParam("\\B_WIDTH", GetSize(bit_ports));
+ cell->setPort(ID(A), port_a);
+ cell->setPort(ID(B), bit_ports);
+ cell->setParam(ID(CONFIG), config_bits);
+ cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits));
+ cell->setParam(ID(A_WIDTH), GetSize(port_a));
+ cell->setParam(ID(B_WIDTH), GetSize(bit_ports));
}
bool eval(RTLIL::Const &result) const