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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-05-21 02:26:52 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-07-28 23:18:38 +0200 |
commit | 19720b970dff017c47805e37745b9fcf29843c45 (patch) | |
tree | b5a56d888b9e8c7530fc456a8748c32bb3feaed3 /kernel/mem.h | |
parent | 37d76deef1229048e145d77b5c75bcc2e0e1cf44 (diff) | |
download | yosys-19720b970dff017c47805e37745b9fcf29843c45.tar.gz yosys-19720b970dff017c47805e37745b9fcf29843c45.tar.bz2 yosys-19720b970dff017c47805e37745b9fcf29843c45.zip |
memory: Introduce $meminit_v2 cell, with EN input.
Diffstat (limited to 'kernel/mem.h')
-rw-r--r-- | kernel/mem.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/kernel/mem.h b/kernel/mem.h index 62403e00c..24c2d64c8 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -69,6 +69,7 @@ struct MemInit : RTLIL::AttrObject { Cell *cell; Const addr; Const data; + Const en; MemInit() : removed(false), cell(nullptr) {} }; @@ -101,7 +102,8 @@ struct Mem : RTLIL::AttrObject { // address ranges, they are combined into one, with the higher-priority // one's data overwriting the other. Running this results in // an inits list equivalent to the original, in which all entries - // cover disjoint (and non-touching) address ranges. + // cover disjoint (and non-touching) address ranges, and all enable + // masks are all-1. void coalesce_inits(); // Checks consistency of this memory and all its ports/inits, using |