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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-12 23:36:28 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-13 00:37:14 +0200 |
| commit | 990c9b8e11446a306ea577ab8154e0cad155c4d1 (patch) | |
| tree | 5fb931d5e759222dddb392dfa53b73d70e763db6 /kernel/mem.h | |
| parent | c862b1dbfbb3a8e1ec90c483a8364550b3fe840c (diff) | |
| download | yosys-990c9b8e11446a306ea577ab8154e0cad155c4d1.tar.gz yosys-990c9b8e11446a306ea577ab8154e0cad155c4d1.tar.bz2 yosys-990c9b8e11446a306ea577ab8154e0cad155c4d1.zip | |
Add proc_rom pass.
Diffstat (limited to 'kernel/mem.h')
| -rw-r--r-- | kernel/mem.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/mem.h b/kernel/mem.h index ae87b1285..8c484274c 100644 --- a/kernel/mem.h +++ b/kernel/mem.h @@ -46,7 +46,7 @@ struct MemRd : RTLIL::AttrObject { std::vector<bool> collision_x_mask; SigSpec clk, en, arst, srst, addr, data; - MemRd() : removed(false), cell(nullptr) {} + MemRd() : removed(false), cell(nullptr), wide_log2(0), clk_enable(false), clk_polarity(true), ce_over_srst(false), clk(State::Sx), en(State::S1), arst(State::S0), srst(State::S0) {} // Returns the address of given subword index accessed by this port. SigSpec sub_addr(int sub) { |