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author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 14:05:38 +0200 |
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committer | GitHub <noreply@github.com> | 2018-08-15 14:05:38 +0200 |
commit | 67b10262975340e0b53f8d1072ac2e1c1f087fb1 (patch) | |
tree | c10a6e56f6f5b61ce3fbff7c165207cc40d704c8 /kernel/modtools.h | |
parent | d8e40c75eb96e7f3c995b2acd018b5cba6005cdd (diff) | |
parent | 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc (diff) | |
download | yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.gz yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.bz2 yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.zip |
Merge pull request #591 from hzeller/virtual-override
Consistent use of 'override' for virtual methods in derived classes.
Diffstat (limited to 'kernel/modtools.h')
-rw-r--r-- | kernel/modtools.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/kernel/modtools.h b/kernel/modtools.h index ffcb48d44..409562eb9 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> @@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor #endif } - virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE { log_assert(module == cell->module); @@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor port_add(cell, port, sig); } - virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE { log_assert(module == mod); @@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor } } - virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE { log_assert(module == mod); auto_reload_module = true; } - virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE + void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE { log_assert(module == mod); auto_reload_module = true; |