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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 11:58:03 +0200 |
| commit | cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch) | |
| tree | 2d417ab32f95d109a0d8438ae7a14acf51783c5b /kernel/modwalker.h | |
| parent | 665759fceee4a0db3e776b7912e976eea2ff29a3 (diff) | |
| download | yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.tar.gz yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.tar.bz2 yosys-cc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121.zip | |
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'kernel/modwalker.h')
| -rw-r--r-- | kernel/modwalker.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/modwalker.h b/kernel/modwalker.h index 6c3da5dd0..efd97379c 100644 --- a/kernel/modwalker.h +++ b/kernel/modwalker.h @@ -88,12 +88,12 @@ struct ModWalker void add_cell(RTLIL::Cell *cell) { if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) add_cell_port(cell, conn.first, sigmap(conn.second), ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first)); } else { - for (auto &conn : cell->connections) + for (auto &conn : cell->connections_) add_cell_port(cell, conn.first, sigmap(conn.second), true, true); } } |