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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-21 18:56:01 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-21 18:56:01 +0100 |
| commit | 03aa3541aeff0ff372672f553c114fb4146c7858 (patch) | |
| tree | bd6c8e759d93f1a954ba2576857354b9a8fff638 /kernel/rtlil.cc | |
| parent | 310b0a0ffa5ca48650c788c77eee0c8b91aa6bad (diff) | |
| parent | 893194689daee52ea870fef839c237c61e14c6c9 (diff) | |
| download | yosys-03aa3541aeff0ff372672f553c114fb4146c7858.tar.gz yosys-03aa3541aeff0ff372672f553c114fb4146c7858.tar.bz2 yosys-03aa3541aeff0ff372672f553c114fb4146c7858.zip | |
Merge pull request #786 from YosysHQ/pmgen
Pattern Matcher Generator and iCE40 DSP Mapper
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8404db5e9..d4aebcda9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2410,6 +2410,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) if (connections_.count("\\Y")) parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]); + if (connections_.count("\\Q")) + parameters["\\WIDTH"] = GetSize(connections_["\\Q"]); + check(); } |