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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:52:50 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:52:50 +0200 |
| commit | 0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc (patch) | |
| tree | 24f6a3cd2c4fa19a41d90cd57b0908b668efeb21 /kernel/rtlil.cc | |
| parent | 0d60902fd97bba4f231f8f600434b8a69562ffff (diff) | |
| parent | e0a67fce12647b4db7125d33264847c0a3781105 (diff) | |
| download | yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.tar.gz yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.tar.bz2 yosys-0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc.zip | |
Merge branch 'master' into eddie/pr1352
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 17be28f78..bd2fd91a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const { std::vector<RTLIL::Cell*> result; - result.reserve(wires_.size()); + result.reserve(cells_.size()); for (auto &it : cells_) if (design->selected(this, it.second)) result.push_back(it.second); @@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const if (width_ != other.width_) return false; + // Without this, SigSpec() == SigSpec(State::S0, 0) will fail + // since the RHS will contain one SigChunk of width 0 causing + // the size check below to fail + if (width_ == 0) + return true; + pack(); other.pack(); |