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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 12:59:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 12:59:05 -0700 |
| commit | 0c9cf892390941d52a3e35b29d509f4ee19ebae1 (patch) | |
| tree | e206fc9b419ec9a098ba916872598eeff902cb52 /kernel/rtlil.cc | |
| parent | 76a72283e2c2c06efb48c66a0528c4412198858e (diff) | |
| parent | b45d06d7a334c4b18e44793b33aaffcaf1f04b21 (diff) | |
| download | yosys-0c9cf892390941d52a3e35b29d509f4ee19ebae1.tar.gz yosys-0c9cf892390941d52a3e35b29d509f4ee19ebae1.tar.bz2 yosys-0c9cf892390941d52a3e35b29d509f4ee19ebae1.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 790ba52a3..f732b56b0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1565,13 +1565,21 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires) void RTLIL::Module::remove(RTLIL::Cell *cell) { + auto it = cells_.find(cell->name); + log_assert(it != cells_.end()); + remove(it); +} + +dict<RTLIL::IdString, RTLIL::Cell*>::iterator RTLIL::Module::remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it) +{ + RTLIL::Cell *cell = it->second; while (!cell->connections_.empty()) cell->unsetPort(cell->connections_.begin()->first); - log_assert(cells_.count(cell->name) != 0); log_assert(refcount_cells_ == 0); - cells_.erase(cell->name); + it = cells_.erase(it); delete cell; + return it; } void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name) |