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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 20:58:37 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 21:11:48 +0200 |
| commit | 458a94059e6738d93a87ddb9af282d0e1d28791d (patch) | |
| tree | 7d2e8430a312360dd5d7049850b5493eb1dc1734 /kernel/rtlil.cc | |
| parent | 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 (diff) | |
| download | yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.tar.gz yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.tar.bz2 yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.zip | |
Support for 'modports' for System Verilog interfaces
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index fadac0872..07dd4bfa0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -654,7 +654,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLI } -RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*> , bool mayfail) +RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail) { if (mayfail) return RTLIL::IdString(); |