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| author | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2018-07-09 16:02:10 +0200 |
|---|---|---|
| committer | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2018-07-09 16:02:10 +0200 |
| commit | 55df7fff19cfaa42197effc31ac8de07f9090924 (patch) | |
| tree | c13d43201477b7c83b2d0ae9e5b7e4df6a8ba790 /kernel/rtlil.cc | |
| parent | da8083dbd07404fb765e0ffebed6f5477b6d99ad (diff) | |
| download | yosys-55df7fff19cfaa42197effc31ac8de07f9090924.tar.gz yosys-55df7fff19cfaa42197effc31ac8de07f9090924.tar.bz2 yosys-55df7fff19cfaa42197effc31ac8de07f9090924.zip | |
removed debug output
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index df6e0af62..5cef90206 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -642,7 +642,6 @@ RTLIL::Module::Module() refcount_cells_ = 0; #ifdef WITH_PYTHON - std::cout << "inserting module with name " << this->name.c_str() << "\n"; RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this)); #endif } |