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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:53:56 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:53:56 +0200 |
| commit | 66fca65b58bfb944cad45da5836613726498e4b7 (patch) | |
| tree | a78b5d92952ea9f95623bb3daf8028d2402d023b /kernel/rtlil.cc | |
| parent | 46af9a0ff7727c2d47b1dc12501e3328cba1f2e9 (diff) | |
| parent | 5ffb0053ec7d53ffc5c57e3277bfbab5d3fddb54 (diff) | |
| download | yosys-66fca65b58bfb944cad45da5836613726498e4b7.tar.gz yosys-66fca65b58bfb944cad45da5836613726498e4b7.tar.bz2 yosys-66fca65b58bfb944cad45da5836613726498e4b7.zip | |
Merge branch 'master' into mmicko/anlogic
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ded1cd60e..bd2fd91a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const if (width_ != other.width_) return false; + // Without this, SigSpec() == SigSpec(State::S0, 0) will fail + // since the RHS will contain one SigChunk of width 0 causing + // the size check below to fail + if (width_ == 0) + return true; + pack(); other.pack(); |