Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin

1 files changed, 9 insertions, 1 deletions

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 1d380135b..bd2fd91a3 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
 {
 	std::vector<RTLIL::Cell*> result;
-	result.reserve(wires_.size());
+	result.reserve(cells_.size());
 	for (auto &it : cells_)
 		if (design->selected(this, it.second))
 			result.push_back(it.second);
@@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT
 	log_assert(other != NULL);
 	log_assert(width_ == other->width_);
 
+	if (rules.empty()) return;
 	unpack();
 	other->unpack();
 
@@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
 	log_assert(other != NULL);
 	log_assert(width_ == other->width_);
 
+	if (rules.empty()) return;
 	unpack();
 	other->unpack();
 
@@ -3552,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
 	if (width_ != other.width_)
 		return false;
 
+	// Without this, SigSpec() == SigSpec(State::S0, 0) will fail
+	//   since the RHS will contain one SigChunk of width 0 causing
+	//   the size check below to fail
+	if (width_ == 0)
+		return true;
+
 	pack();
 	other.pack();