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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-24 22:47:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-24 23:10:58 +0200 |
| commit | 6aa792c864444324a1b140c2b63bd860f0cc3914 (patch) | |
| tree | 07b2bf3003864337df616a21374c046ddc352c62 /kernel/rtlil.cc | |
| parent | 7a608437c65e9646ed229055d61b310e7d93e37e (diff) | |
| download | yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.gz yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.tar.bz2 yosys-6aa792c864444324a1b140c2b63bd860f0cc3914.zip | |
Replaced more old SigChunk programming patterns
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8e509f360..f741e2a34 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1999,6 +1999,14 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const return true; } +bool RTLIL::SigSpec::is_wire() const +{ + cover("kernel.rtlil.sigspec.is_wire"); + + pack(); + return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_; +} + bool RTLIL::SigSpec::is_fully_const() const { cover("kernel.rtlil.sigspec.is_fully_const"); @@ -2104,6 +2112,15 @@ RTLIL::Const RTLIL::SigSpec::as_const() const return RTLIL::Const(); } +RTLIL::Wire *RTLIL::SigSpec::as_wire() const +{ + cover("kernel.rtlil.sigspec.as_wire"); + + pack(); + assert(is_wire()); + return chunks_[0].wire; +} + bool RTLIL::SigSpec::match(std::string pattern) const { cover("kernel.rtlil.sigspec.match"); |