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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-25 13:17:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-25 13:17:22 -0700 |
| commit | 6b90d3cf6cd433420ed46e0cc31fc71773f3117b (patch) | |
| tree | b443709301ab64f909969018c661969f49e1aff3 /kernel/rtlil.cc | |
| parent | bf83c074c82756b1cd23a9c3998b6c4d535dae29 (diff) | |
| parent | ddc1a4488e9fc10f557e4260df0becbc1cf43f72 (diff) | |
| download | yosys-6b90d3cf6cd433420ed46e0cc31fc71773f3117b.tar.gz yosys-6b90d3cf6cd433420ed46e0cc31fc71773f3117b.tar.bz2 yosys-6b90d3cf6cd433420ed46e0cc31fc71773f3117b.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d0fa88890..b3214579d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3237,7 +3237,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) remove(width, width_ - width); if (width_ < width) { - RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; + RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; if (!is_signed) padding = RTLIL::State::S0; while (width_ < width) |