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authorEddie Hung <eddie@fpgeh.com>2019-06-18 12:47:12 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-18 12:47:12 -0700
commit7324a4c2cd0132f792f4fade1a77aeceae46bd85 (patch)
tree4510f12308d725eeeac2b2635cf73dc08823f80c /kernel/rtlil.cc
parent6a4025b5eef3ea96a8a7cdb0046cb2193cfa08e5 (diff)
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Remove iterator based Module::remove as per @cliffordwolf
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r--kernel/rtlil.cc13
1 files changed, 3 insertions, 10 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f732b56b0..3990ec283 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1565,21 +1565,14 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
void RTLIL::Module::remove(RTLIL::Cell *cell)
{
- auto it = cells_.find(cell->name);
- log_assert(it != cells_.end());
- remove(it);
-}
-
-dict<RTLIL::IdString, RTLIL::Cell*>::iterator RTLIL::Module::remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it)
-{
- RTLIL::Cell *cell = it->second;
while (!cell->connections_.empty())
cell->unsetPort(cell->connections_.begin()->first);
+ auto it = cells_.find(cell->name);
+ log_assert(it != cells_.end());
log_assert(refcount_cells_ == 0);
- it = cells_.erase(it);
+ cells_.erase(it);
delete cell;
- return it;
}
void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)