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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-19 13:59:08 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-19 13:59:08 +0100 |
| commit | 76c5d863c52253a5709f44e0608c53a8c33ab3b5 (patch) | |
| tree | 7cb4d36e4b10f4dd468f58255ad5dba39a585dbd /kernel/rtlil.cc | |
| parent | e13a45ae61e05705d9ab6890da60737bd05eb24d (diff) | |
| download | yosys-76c5d863c52253a5709f44e0608c53a8c33ab3b5.tar.gz yosys-76c5d863c52253a5709f44e0608c53a8c33ab3b5.tar.bz2 yosys-76c5d863c52253a5709f44e0608c53a8c33ab3b5.zip | |
Added equiv_make command
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ec61cb529..52293da29 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1618,6 +1618,15 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a return cell; } +RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y) +{ + RTLIL::Cell *cell = addCell(name, "$equiv"); + cell->setPort("\\A", sig_a); + cell->setPort("\\B", sig_b); + cell->setPort("\\Y", sig_y); + return cell; +} + RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity) { RTLIL::Cell *cell = addCell(name, "$sr"); |