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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 14:38:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:21 +0200 |
| commit | 7ac9dc7f6eab40b3853583848933c4a8a94df9c9 (patch) | |
| tree | bf27c3ea022ca9b9d06a5a9dc2c6b6d336fa6631 /kernel/rtlil.cc | |
| parent | b03aec6e3212a387e3d255583476d472d16663f1 (diff) | |
| download | yosys-7ac9dc7f6eab40b3853583848933c4a8a94df9c9.tar.gz yosys-7ac9dc7f6eab40b3853583848933c4a8a94df9c9.tar.bz2 yosys-7ac9dc7f6eab40b3853583848933c4a8a94df9c9.zip | |
Added RTLIL::Module::connections()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ce4ecea6f..1638682c1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -883,6 +883,11 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs connections_.push_back(RTLIL::SigSig(lhs, rhs)); } +const std::vector<RTLIL::SigSig> &RTLIL::Module::connections() +{ + return connections_; +} + void RTLIL::Module::fixup_ports() { std::vector<RTLIL::Wire*> all_ports; |