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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-01 12:26:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-01 12:26:55 +0200 |
| commit | 8a66bd30c67c753149a195b951a3191d8e5e3304 (patch) | |
| tree | 3c48790ce444bc2de95d20b01181f6d871e53fbb /kernel/rtlil.cc | |
| parent | 8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a (diff) | |
| download | yosys-8a66bd30c67c753149a195b951a3191d8e5e3304.tar.gz yosys-8a66bd30c67c753149a195b951a3191d8e5e3304.tar.bz2 yosys-8a66bd30c67c753149a195b951a3191d8e5e3304.zip | |
Update more stuff to use get_src_attribute() and set_src_attribute()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index faddcd994..9539861cd 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1643,7 +1643,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth cell->parameters["\\Y_WIDTH"] = sig_y.size(); \ cell->setPort("\\A", sig_a); \ cell->setPort("\\Y", sig_y); \ - if (!src.empty()) cell->attributes["\\src"] = src; \ + cell->set_src_attribute(src); \ return cell; \ } \ RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \ |