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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-17 09:38:56 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-17 09:38:56 +0200 |
| commit | 99100f367d9239b4607a7fee05855a5f34be4467 (patch) | |
| tree | d858fc477e922432708583ce687a8ac8b7a18479 /kernel/rtlil.cc | |
| parent | 9f7a5b4ef92357761a3526fdc1c8171d8be9888c (diff) | |
| download | yosys-99100f367d9239b4607a7fee05855a5f34be4467.tar.gz yosys-99100f367d9239b4607a7fee05855a5f34be4467.tar.bz2 yosys-99100f367d9239b4607a7fee05855a5f34be4467.zip | |
Added "rename -top new_name"
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5deef8507..7cd2dd4bb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -316,6 +316,21 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) return modules_.count(name) ? modules_.at(name) : NULL; } +RTLIL::Module *RTLIL::Design::top_module() +{ + RTLIL::Module *module = nullptr; + int module_count = 0; + + for (auto mod : selected_modules()) { + if (mod->get_bool_attribute("\\top")) + return mod; + module_count++; + module = mod; + } + + return module_count == 1 ? module : nullptr; +} + void RTLIL::Design::add(RTLIL::Module *module) { log_assert(modules_.count(module->name) == 0); |