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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:08:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:08:58 -0700 |
| commit | 99ff7b5c8c74371841e74d81b7a0d63cd9487e61 (patch) | |
| tree | 72e3b31c807eef5f39c797c8eb3530da98f78980 /kernel/rtlil.cc | |
| parent | 31b0dee7f3f12c76b721f2fa8e11c722307abb09 (diff) | |
| parent | 3b8f3a93ada563fbae62772b0bf642bb54170954 (diff) | |
| download | yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.tar.gz yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.tar.bz2 yosys-99ff7b5c8c74371841e74d81b7a0d63cd9487e61.zip | |
Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a5fbfeda4..94dbf31c0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3438,7 +3438,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) if (width_ < width) { RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; - if (padding != RTLIL::State::Sx && !is_signed) + if (!is_signed) padding = RTLIL::State::S0; while (width_ < width) append(padding); |