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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:53:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:53:20 -0700 |
| commit | a5ac33f230b5dd20273f6636e5b573ef0478b8f9 (patch) | |
| tree | 6f67a20084e1490fec10824cf4ff9eb4c6fe14e8 /kernel/rtlil.cc | |
| parent | aae2b9fd9c8dc915fadacc24962436dd7aedff36 (diff) | |
| parent | 0acc51c3d82f65f73fa9e475c6fc41beabd925a6 (diff) | |
| download | yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.tar.gz yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.tar.bz2 yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.zip | |
Merge branch 'master' into eddie/abc_to_abc9
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ded1cd60e..bd2fd91a3 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const if (width_ != other.width_) return false; + // Without this, SigSpec() == SigSpec(State::S0, 0) will fail + // since the RHS will contain one SigChunk of width 0 causing + // the size check below to fail + if (width_ == 0) + return true; + pack(); other.pack(); |